// Generated register defines for pulpissimo_padframe_all_pads_config

// Licensing information found in source file:

#ifndef _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_
#define _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_

#ifdef __cplusplus
extern "C" {
#endif
// Register width
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PARAM_REG_WIDTH 32

// Read-only IP Information register
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_REG_OFFSET 0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_MASK 0xffff
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_OFFSET 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_HW_VERSION_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_MASK 0xffff
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_OFFSET 16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_INFO_PADCOUNT_OFFSET })

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_REG_OFFSET 0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io00. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_REG_OFFSET 0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_GPIO_GPIO00 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO00_MUX_SEL_PAD_IO00_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_REG_OFFSET 0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io01. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_REG_OFFSET 0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_GPIO_GPIO01 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO01_MUX_SEL_PAD_IO01_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_REG_OFFSET 0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io02. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_REG_OFFSET 0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_GPIO_GPIO02 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO02_MUX_SEL_PAD_IO02_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_REG_OFFSET 0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io03. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_REG_OFFSET 0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_GPIO_GPIO03 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO03_MUX_SEL_PAD_IO03_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_REG_OFFSET 0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io04. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_REG_OFFSET 0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_GPIO_GPIO04 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO04_MUX_SEL_PAD_IO04_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_REG_OFFSET 0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io05. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_REG_OFFSET 0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_GPIO_GPIO05 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO05_MUX_SEL_PAD_IO05_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_REG_OFFSET 0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io06. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_REG_OFFSET 0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_GPIO_GPIO06 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO06_MUX_SEL_PAD_IO06_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_REG_OFFSET 0x3c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io07. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_REG_OFFSET 0x40
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_GPIO_GPIO07 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO07_MUX_SEL_PAD_IO07_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_REG_OFFSET 0x44
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io08. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_REG_OFFSET 0x48
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_GPIO_GPIO08 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO08_MUX_SEL_PAD_IO08_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_REG_OFFSET 0x4c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io09. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_REG_OFFSET 0x50
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_GPIO_GPIO09 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO09_MUX_SEL_PAD_IO09_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_REG_OFFSET 0x54
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io10. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_REG_OFFSET 0x58
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_GPIO_GPIO10 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO10_MUX_SEL_PAD_IO10_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_REG_OFFSET 0x5c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io11. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_REG_OFFSET 0x60
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_GPIO_GPIO11 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO11_MUX_SEL_PAD_IO11_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_REG_OFFSET 0x64
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io12. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_REG_OFFSET 0x68
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_GPIO_GPIO12 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO12_MUX_SEL_PAD_IO12_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_REG_OFFSET 0x6c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io13. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_REG_OFFSET 0x70
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_GPIO_GPIO13 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO13_MUX_SEL_PAD_IO13_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_REG_OFFSET 0x74
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io14. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_REG_OFFSET 0x78
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_GPIO_GPIO14 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO14_MUX_SEL_PAD_IO14_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_REG_OFFSET 0x7c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io15. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_REG_OFFSET 0x80
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_GPIO_GPIO15 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO15_MUX_SEL_PAD_IO15_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_REG_OFFSET 0x84
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io16. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_REG_OFFSET 0x88
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_GPIO_GPIO16 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO16_MUX_SEL_PAD_IO16_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_REG_OFFSET 0x8c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io17. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_REG_OFFSET 0x90
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_GPIO_GPIO17 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO17_MUX_SEL_PAD_IO17_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_REG_OFFSET 0x94
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io18. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_REG_OFFSET 0x98
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_GPIO_GPIO18 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO18_MUX_SEL_PAD_IO18_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_REG_OFFSET 0x9c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io19. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_REG_OFFSET 0xa0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_GPIO_GPIO19 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO19_MUX_SEL_PAD_IO19_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_REG_OFFSET 0xa4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io20. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_REG_OFFSET 0xa8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_GPIO_GPIO20 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO20_MUX_SEL_PAD_IO20_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_REG_OFFSET 0xac
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io21. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_REG_OFFSET 0xb0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_GPIO_GPIO21 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO21_MUX_SEL_PAD_IO21_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_REG_OFFSET 0xb4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io22. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_REG_OFFSET 0xb8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_GPIO_GPIO22 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO22_MUX_SEL_PAD_IO22_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_REG_OFFSET 0xbc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io23. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_REG_OFFSET 0xc0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_GPIO_GPIO23 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO23_MUX_SEL_PAD_IO23_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_REG_OFFSET 0xc4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io24. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_REG_OFFSET 0xc8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_GPIO_GPIO24 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO24_MUX_SEL_PAD_IO24_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_REG_OFFSET 0xcc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io25. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_REG_OFFSET 0xd0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_GPIO_GPIO25 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO25_MUX_SEL_PAD_IO25_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_REG_OFFSET 0xd4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io26. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_REG_OFFSET 0xd8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_GPIO_GPIO26 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO26_MUX_SEL_PAD_IO26_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_REG_OFFSET 0xdc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io27. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_REG_OFFSET 0xe0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_GPIO_GPIO27 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO27_MUX_SEL_PAD_IO27_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_REG_OFFSET 0xe4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io28. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_REG_OFFSET 0xe8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_GPIO_GPIO28 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO28_MUX_SEL_PAD_IO28_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_REG_OFFSET 0xec
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io29. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_REG_OFFSET 0xf0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_GPIO_GPIO29 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO29_MUX_SEL_PAD_IO29_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_REG_OFFSET 0xf4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io30. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_REG_OFFSET 0xf8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_GPIO_GPIO30 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO30_MUX_SEL_PAD_IO30_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

// Pad signal configuration.
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_REG_OFFSET 0xfc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_CHIP2PAD_BIT 0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_PULL_EN_BIT 1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_RX_EN_BIT 2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_CFG_TX_EN_BIT 3

// Pad signal port multiplex selection for pad pad_io31. The programmed value
// defines which port
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_REG_OFFSET 0x100
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_MASK \
  0x3f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_OFFSET \
  0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_FIELD \
  ((bitfield_field32_t) { .mask = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_MASK, .index = PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_OFFSET })
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_REGISTER \
  0x0
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA0 \
  0x1
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA1 \
  0x2
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA2 \
  0x3
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA3 \
  0x4
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA4 \
  0x5
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA5 \
  0x6
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA6 \
  0x7
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA7 \
  0x8
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA8 \
  0x9
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_DATA9 \
  0xa
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_HSYNC \
  0xb
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_PCLK \
  0xc
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_CPI0_VSYNC \
  0xd
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_GPIO_GPIO31 \
  0xe
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2C0_SCL \
  0xf
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2C0_SDA \
  0x10
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SCK \
  0x11
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD0 \
  0x12
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_SD1 \
  0x13
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_MASTER_WS \
  0x14
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SCK \
  0x15
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD0 \
  0x16
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_SD1 \
  0x17
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_I2S0_SLAVE_WS \
  0x18
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN0 \
  0x19
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN1 \
  0x1a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN2 \
  0x1b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_CSN3 \
  0x1c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SCK \
  0x1d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO0 \
  0x1e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO1 \
  0x1f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO2 \
  0x20
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_QSPIM0_SDIO3 \
  0x21
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDCLK \
  0x22
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDCMD \
  0x23
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA0 \
  0x24
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA1 \
  0x25
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA2 \
  0x26
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_SDIO0_SDDATA3 \
  0x27
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT0 \
  0x28
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT1 \
  0x29
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT2 \
  0x2a
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER0_OUT3 \
  0x2b
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT0 \
  0x2c
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT1 \
  0x2d
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT2 \
  0x2e
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER1_OUT3 \
  0x2f
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT0 \
  0x30
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT1 \
  0x31
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT2 \
  0x32
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER2_OUT3 \
  0x33
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT0 \
  0x34
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT1 \
  0x35
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT2 \
  0x36
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_TIMER3_OUT3 \
  0x37
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_UART0_RX \
  0x38
#define PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_PAD_IO31_MUX_SEL_PAD_IO31_MUX_SEL_VALUE_PORT_UART0_TX \
  0x39

#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _PULPISSIMO_PADFRAME_ALL_PADS_CONFIG_REG_DEFS_
// End generated register defines for pulpissimo_padframe_all_pads_config